The Clemson University Instruction-Level Parallelism Laboratory (or ILP Lab) is jointly directed by Dr. Mark Smotherman of Computer Sciences Department and Dr. Manoj Franklin of Electrical and Computer Engineering Department. We study all aspects of computer architecture to improve processor performance. Most of these studies examine possible methods for exploiting the existing parallelism inherent in a single, sequential program. ILP techniques offer the potential for improving performance for existing architectures, a possibility of great interest to the computer hardware industry.
Recent studies have looked at branch prediction, caching strategies, and dynamic scheduling of instructions for out-of-order execution. Research and evaluation of new designs are conducted using execution-based simulators to study the design's performance running real-world software. Currently, these simulators run on Digital DECstation 5000s, although the lab will be adding Alpha-based workstations in the near future.
Students in the lab are encouraged to pursue their own research interests, a situation which results in frequent publishing opportunities for the motivated student.
Block-Level Prediction for Wide-Issue Superscalar Processors Proceedings of 1st International Conference on Algorithms and Architectures for Parallel Processing, Vol. 1, pp. 143-152, 1995.
Control Flow Prediction with Tree-Like Subgraphs for Superscalar Processors Proceedings of 28th Annual International Symposium on Microarchitecture (MICRO-28), pp. 258-263, 1995.
Improving CISC Instruction Decoding Performance Using a Fill Unit Proceedings of 28th Annual International Symposium on Microarchitecture (MICRO-28), 1995.
Multi-Version Caches for Multiscalar Processors Proceedings of 1st International Conference on High Performance Computing, 1995.
ARB: A Hardware Mechanism for Dynamic Memory Disambiguation IEEE Transactions on Computers, Vol. 45, No. 5, pp. 552-571, May 1996.
PEWs: A Decentralized Dynamic Scheduler for ILP Processing Proceedings of International Conference on Parallel Processing (ICPP), Vol. I, pp. 239-246, 1996