This file lists the ISA of the processor for simulation. The 
instructions are listed according to type (integer/branch). 
Example inputs are provided for all the instructions. After 
the instruction, the output register corresponding to the 
example inputs is also provided. Thus the listing format is:

[instruction] [sample arguments] [output reg] (comments)


The following registers are used in this architecture:

- R0-R31 (integer registers)
- F0-F30 (floating point registers)
- HI_LO  (hi and lo registers: hold 64-bit multiplication result)
- FCC    (floating point condition code register)


For simplicity you can assume that the processor has 65 registers
corresponding to the following logical registers:

  0..31:  R0..R31
  32..62: F0..F30
  63:     HI_LO   (treat this pair as one register)
  64:     FCC

HI_LO and FCC are used in some instructions implicitly as either
input operands or as output operands. This information is written
next to the instructions below.


conditional instructions
========================

j 	1234		[-]	
jal	1234	 	[-]
jr      r31		[-]
jalr	r31,r2		[r31]
beq	r4,r3,1234	[-]
bne	r4,r3,1234	[-]
blez	r4,1234		[-]
bgtz	r4,1234		[-]
bltz	r4,1234		[-]
bgez	r4,1234		[-]
bc1f	32		[-]  (Input reg: FCC)
bc1t	32		[-]  (Input reg: FCC)



load instructions
=================

lb	r4,1234(r2)	[r4]	
lbu	r4,1234(r2)	[r4]
lh	r4,1234(r2)	[r4]
lhu	r4,1234(r2)	[r4]
lw	r4,1234(r2)	[r4]
l.s	f3,1234(r2)	[f3]
l.d	f3,1234(r2)	[f3]


store instructions
==================

sb	r4,0(r2)	[-]
sh	r4,0(r2)	[-]
sw	r4,0(r2)	[-]
s.s	f3,0(r2)	[-]
s.d	f3,0(r2)	[-]


integer instructions
====================

add	r4,r3,r22	[r4]
addi	r4,r3,1234	[r4]
addu	r4,r3,r2	[r4]
addiu	r4,r3,1234	[r4]
sub	r4,r3,r2	[r4]
subu	r4,r3,r2	[r4]
mult	r4,r3		[HI_LO] (Output reg: HI_LO)
div	r4,r3		[HI_LO] (Output reg: HI_LO)
divu	r4,r3		[HI_LO] (Output reg: HI_LO)
mfhi	r4		[r4]    (Input reg:  HI_LO)
mflo	r4		[r4]    (Input reg:  HI_LO)
lui	r4,1234		[r4]
mfc1	r4,f0		[r4]
dmfc1	r4,f0		[r4]
mtc1	r4,f0		[f0]
dmtc1	r4,f0		[f0]


logical instructions
====================

and	r4,r3,r2	[r4]
andi	r4,r3,7		[r4]
or	r4,r3,r2	[r4]
ori	r4,r3,1234	[r4]	
xor	r4,r3,r2	[r4]
xori	r4,r3,1234	[r4]
nor	r4,r3,r2	[r4]
sll	r4,r3,1234	[r4]
sllv	r4,r3,r2	[r4]
srl	r4,r3,1234	[r4]
srlv	r4,r3,r2	[r4]
sra	r4,r3,1234	[r4]
srav	r4,r3,r2	[r4]
slt	r4,r3,r2	[r4]
slti	r4,r3,1234	[r4]
sltu	r4,r3,r2	[r4]
sltiu	r4,r3,1234	[r4]


floating point instructions
===========================

add.s	f0,f2,f1	[f0]	
add.d	f0,f2,f1	[f0]
sub.s	f0,f2,f1	[f0]
sub.d	f0,f2,f1	[f0]
mul.s	f0,f2,f1	[f0]
mul.d	f0,f2,f1	[f0]
div.d	f0,f2,f1	[f0]
mov.d	f0,f1		[f0]
neg.d	f0,f1		[f0]
cvt.s.d	f0,f1		[f0]
cvt.s.w	f0.f1		[f0]
cvt.d.s	f0,f1		[f0]
cvt.d.w	f0,f1		[f0]
cvt.w.d	f0,f1		[f0]
c.eq.d	f0,f1		[FCC]   (Output reg: FCC)
c.lt.d	f0,f1		[FCC]   (Output reg: FCC)
c.le.d	f0,f1		[FCC]   (Output reg: FCC)
sqrt.d	f0,f1		[f0]


miscellaneous instructions (treat all as nop)
==========================

syscall			[-]
nop			[-]